Pixel circuit, display panel, display device, and driving method

ABSTRACT

A pixel circuit, a display panel, a display device, and a method of driving a display device are provided. The pixel circuit includes a driving sub-circuit, a first data writing sub-circuit, a second data writing sub-circuit, and a storage sub-circuit. The first data writing sub-circuit is configured to write a first data voltage to a first terminal of the storage sub-circuit in a case of being turned on under control of a first data scanning signal; the second data writing sub-circuit is configured to write a second data voltage to a second terminal of the storage sub-circuit in a case of being turned on under control of a second data scanning signal; and the driving sub-circuit is configured to drive a light emitting element to emit light under control of the voltage at the first terminal of the storage sub-circuit.

The present application claims priority to Chinese patent applicationNo. 201810353782.5, filed on Apr. 19, 2018, the entire disclosure ofwhich is incorporated herein by reference as part of the presentapplication.

TECHNICAL FIELD

Embodiments of the present disclosure relate to a pixel circuit, adisplay panel, a display device, and a method of driving a displaydevice.

BACKGROUND

Organic light emitting diode display panels have been widely used.Because the organic light emitting diode display panels can activelyemit light, there is no need to additionally set a backlight, therebymeeting the demand of users for display devices of light weight and thinthickness.

With the enhancement of requirements of the users, techniques have beendeveloped to change the contrast ratio of display devices according tothe change of ambient brightness. For example, high contrast ratio andlow brightness are required for nighttime display, and low contrastratio and high brightness are required for daytime display.

SUMMARY

At least some embodiments of the present disclosure provide a pixelcircuit, a display panel, a display device, and a method of driving adisplay device. The pixel circuit can realize two operation modes, i.e.,high brightness and high contrast ratio, and a structure thereof issimple and is easy to be implemented.

At least some embodiments of the present disclosure provide a pixelcircuit, which includes: a driving sub-circuit, a first data writingsub-circuit, a second data writing sub-circuit, and a storagesub-circuit. The first data writing sub-circuit is electricallyconnected to a first terminal of the storage sub-circuit, and isconfigured to write a first data voltage to the first terminal of thestorage sub-circuit in a case of being turned on under control of afirst data scanning signal; the second data writing sub-circuit iselectrically connected to a second terminal of the storage sub-circuit,and is configured to write a second data voltage to the second terminalof the storage sub-circuit in a case of being turned on under control ofa second data scanning signal, so as to control a voltage at the firstterminal of the storage sub-circuit based on the second data voltage;the first terminal of the storage sub-circuit is further electricallyconnected to a control terminal of the driving sub-circuit; and thedriving sub-circuit is configured to drive a light emitting element toemit light under control of the voltage at the first terminal of thestorage sub-circuit.

For example, in the pixel circuit provided by some embodiments of thepresent disclosure, the second data writing sub-circuit includes a firstdata writing transistor, a gate electrode of the first data writingtransistor is configured to receive the second data scanning signal, afirst electrode of the first data writing transistor is configured toreceive the second data voltage, and a second electrode of the firstdata writing transistor is electrically connected to the second terminalof the storage sub-circuit.

For example, in the pixel circuit provided by some embodiments of thepresent disclosure, the first data writing transistor is turned on in acase where the second data scanning signal is at a first level, thefirst data writing transistor is turned off in a case where the seconddata scanning signal is at a second level, and the first level isopposite to the second level.

For example, in the pixel circuit provided by some embodiments of thepresent disclosure, the first data writing transistor is a P-typetransistor.

For example, in the pixel circuit provided by some embodiments of thepresent disclosure, a control terminal of the first data writingsub-circuit is configured to receive the first data scanning signal, thecontrol terminal of the first data writing sub-circuit includes a firstcontrol sub-terminal and a second control sub-terminal, the first datascanning signal includes a first data scanning sub-signal and a seconddata scanning sub-signal, the first control sub-terminal is configuredto receive the first data scanning sub-signal, and the second controlsub-terminal is configured to receive the second data scanningsub-signal.

For example, in the pixel circuit provided by some embodiments of thepresent disclosure, the first data writing sub-circuit includes anN-type data writing transistor and a P-type data writing transistor, afirst electrode of the N-type data writing transistor and a firstelectrode of the P-type data writing transistor are both configured toreceive the first data voltage, a second electrode of the N-type datawriting transistor and a second electrode of the P-type data writingtransistor are both electrically connected to the first terminal of thestorage sub-circuit, the first control sub-terminal includes a gateelectrode of the N-type data writing transistor, and the second controlsub-terminal includes a gate electrode of the P-type data writingtransistor.

For example, the pixel circuit provided by some embodiments of thepresent disclosure further includes a reset sub-circuit, a first outputterminal of the reset sub-circuit is electrically connected to thesecond terminal of the storage sub-circuit, a second output terminal ofthe reset sub-circuit is electrically connected to an anode of the lightemitting element, and the reset sub-circuit is configured to reset thesecond terminal of the storage sub-circuit under control of a firstreset control signal, and to reset the anode of the light emittingelement under control of a second reset control signal.

For example, in the pixel circuit provided by some embodiments of thepresent disclosure, an input terminal of the reset sub-circuit iselectrically connected to a first reference level signal terminal and asecond reference level signal terminal, the reset sub-circuit isconfigured to write a first reference level signal of the firstreference level signal terminal to the second terminal of the storagesub-circuit under control of the first reset control signal, so as toreset the second terminal of the storage sub-circuit, and the resetsub-circuit is further configured to write a second reference levelsignal of the second reference level signal terminal to the anode of thelight emitting element under control of the second reset control signal,so as to reset the anode of the light emitting element.

For example, in the pixel circuit provided by some embodiments of thepresent disclosure, the reset sub-circuit includes a first resettransistor and a second reset transistor, the input terminal of thereset sub-circuit includes a first electrode of the first resettransistor and a first electrode of the second reset transistor, thefirst output terminal includes a second electrode of the first resettransistor, the second output terminal includes a second electrode ofthe second reset transistor, a gate electrode of the first resettransistor is configured to receive the first reset control signal, thefirst electrode of the first reset transistor is electrically connectedto the first reference level signal terminal, the second electrode ofthe first reset transistor is electrically connected to the secondterminal of the storage sub-circuit, a gate electrode of the secondreset transistor is configured to receive the second reset controlsignal, the first electrode of the second reset transistor iselectrically connected to the second reference level signal terminal,and the second electrode of the second reset transistor is electricallyconnected to the anode of the light emitting element.

For example, the pixel circuit provided by some embodiments of thepresent disclosure further includes a light emitting controlsub-circuit, and the light emitting control sub-circuit is configured toelectrically connect or disconnect the driving sub-circuit and the lightemitting element under control of a light emitting control signal.

For example, in the pixel circuit provided by some embodiments of thepresent disclosure, the light emitting control sub-circuit includes alight emitting control transistor, a gate electrode of the lightemitting control transistor is configured to receive the light emittingcontrol signal, a first electrode of the light emitting controltransistor is electrically connected to a first level signal terminal,and a second electrode of the light emitting control transistor iselectrically connected to the driving sub-circuit.

For example, in the pixel circuit provided by some embodiments of thepresent disclosure, the driving sub-circuit includes a drivingtransistor, a first electrode of the driving transistor is electricallyconnected to the light emitting control sub-circuit, a second electrodeof the driving transistor is electrically connected to an anode of thelight emitting element, and the control terminal of the drivingsub-circuit includes a gate electrode of the driving transistor, thegate electrode of the driving transistor is electrically connected tothe first terminal of the storage sub-circuit, and a cathode of thelight emitting element is electrically connected to a second levelsignal terminal.

For example, in the pixel circuit provided by some embodiments of thepresent disclosure, the storage sub-circuit includes a storagecapacitor, the first terminal of the storage sub-circuit includes afirst terminal of the storage capacitor, and the second terminal of thestorage sub-circuit includes a second terminal of the storage capacitor.

At least some embodiments of the present disclosure further provide adisplay panel, which includes the pixel circuit according to any one ofthe above-mentioned embodiments.

For example, the display panel provided by some embodiments of thepresent disclosure further includes a plurality of pixel units, theplurality of pixel units are arranged in a plurality of rows and aplurality of columns, and the pixel circuit is disposed in each of theplurality of pixel units.

For example, in the display panel provided by some embodiments of thepresent disclosure, the plurality of rows of pixel units in theplurality of pixel units are in one-to-one correspondence with aplurality of gate line groups, respectively, and the plurality ofcolumns of pixel units in the plurality of pixel units are in one-to-onecorrespondence with a plurality of data line groups, respectively; eachof the plurality of gate line groups includes a first gate line and asecond gate line, the first gate line is configured to provide the firstdata scanning signal, and the second gate line is configured to providethe second data scanning signal; in pixel units of a same row, the firstdata writing sub-circuit in each of the pixel units is electricallyconnected to the first gate line to receive the first data scanningsignal, and the second data writing sub-circuit in each of the pixelunits is electrically connected to the second gate line to receive thesecond data scanning signal; each of the plurality of data line groupsincludes a first data line and a second data line, the first data lineis configured to provide the first data voltage, and the second dataline is configured to provide the second data voltage; and in pixelunits of a same column, the first data writing sub-circuit in each ofthe pixel units is electrically connected to the first data line toreceive the first data voltage, and the second data writing sub-circuitin each of the pixel units is electrically connected to the second dataline to receive the second data voltage.

For example, in the display panel provided by some embodiments of thepresent disclosure, in a case where a control terminal of the first datawriting sub-circuit includes a first control sub-terminal and a secondcontrol sub-terminal, the first gate line includes a first gate sub-lineand a second gate sub-line, and in the pixel units of the same row, thefirst control sub-terminal of the first data writing sub-circuit in eachof the pixel units is electrically connected to the first gate sub-line,and the second control sub-terminal of the first data writingsub-circuit in each of the pixel units is electrically connected to thesecond gate sub-line.

At least some embodiments of the present disclosure further provide adisplay device, which includes the display panel according to any one ofthe above-mentioned embodiments.

For example, the display device provided by some embodiments of thepresent disclosure further includes a photosensitive element, thephotosensitive element is configured to detect brightness of anenvironment in which the display device is located, generate a firsttrigger signal to control the display device to be in a first operationmode in a case where the brightness is higher than or equal to a presetbrightness, and generate a second trigger signal to control the displaydevice to be in a second operation mode in a case where the brightnessis lower than the preset brightness.

For example, in the display device provided by some embodiments of thepresent disclosure, display brightness of the display device in thefirst operation mode is higher than display brightness of the displaydevice in the second operation mode.

For example, the display device provided by some embodiments of thepresent disclosure further includes a data driver, the data driver iselectrically connected to the pixel circuit in the display panel via afirst data line and a second data line, provide the first data voltageto the pixel circuit via the first data line, and provide the seconddata voltage to the pixel circuit via the second data line.

For example, the display device provided by some embodiments of thepresent disclosure further includes a gate driver, and the gate driveris configured to provide the first data scanning signal and the seconddata scanning signal to the pixel circuit in the display panel.

At least some embodiments of the present disclosure further provide amethod of driving the display device according to any one of theabove-mentioned embodiments, in a case where the photosensitive elementgenerates the first trigger signal, an operation period of the displaypanel includes a charging phase, a voltage jump phase, and a lightemitting phase, and the method includes: in the charging phase,controlling the first data writing sub-circuit to write the first datavoltage to the first terminal of the storage sub-circuit; in the voltagejump phase, controlling the second data writing sub-circuit to write thesecond data voltage to the second terminal of the storage sub-circuit,so as to control the voltage at the first terminal of the storagesub-circuit, in which the voltage at the first terminal of the storagesub-circuit during the charging phase is different from the voltage atthe first terminal of the storage sub-circuit during the voltage jumpphase; and in the light emitting phase, the driving sub-circuit drivingthe light emitting element to emit light based on the voltage at thefirst terminal of the storage sub-circuit.

At least some embodiments of the present disclosure further provide amethod of driving the display device according to any one of theabove-mentioned embodiments, in a case where the photosensitive elementgenerates the second trigger signal, an operation period of the displaypanel includes a charging phase and a light emitting phase, and themethod includes: in the charging phase, controlling the first datawriting sub-circuit to write the first data voltage to the firstterminal of the storage sub-circuit; and in the light emitting phase,the driving sub-circuit driving the light emitting element to emit lightbased on the voltage at the first terminal of the storage sub-circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to clearly illustrate the technical solutions of theembodiments of the disclosure, the drawings of the embodiments will bebriefly described in the following: it is obvious that the describeddrawings are only related to some embodiments of the disclosure and thusare not limitative to the disclosure.

FIG. 1A is a schematic diagram of a pixel circuit provided by someembodiments of the present disclosure;

FIG. 1B is a schematic diagram of another pixel circuit provided by someembodiments of the present disclosure;

FIG. 2A is a schematic diagram of a circuit structure of a pixel circuitprovided by some embodiments of the present disclosure;

FIG. 2B is a schematic diagram of a circuit structure of another pixelcircuit provided by some embodiments of the present disclosure;

FIG. 3A is a signal timing diagram of a pixel circuit during operationprovided by some embodiments of the present disclosure;

FIG. 3B is another signal timing diagram of a pixel circuit duringoperation provided by some embodiments of the present disclosure;

FIG. 3C is further another signal timing diagram of a pixel circuitduring operation provided by some embodiments of the present disclosure;

FIG. 4A is a diagram showing relationship of brightness and a voltagebetween two terminals of a light emitting element provided by someembodiments of the present disclosure;

FIG. 4B is a diagram showing relationship of brightness and a voltagebetween two terminals of another light emitting element provided by someembodiments of the present disclosure;

FIG. 5 is a schematic diagram of a display panel provided by someembodiments of the present disclosure;

FIG. 6 is a schematic diagram of a display device provided by someembodiments of the present disclosure; and

FIG. 7 is a schematic flowchart of a method of driving a display deviceprovided by some embodiments of the present disclosure.

DETAILED DESCRIPTION

In order to make objects, technical details and advantages of theembodiments of the disclosure apparent, the technical solutions of theembodiments will be described in a clearly and fully understandable wayin connection with the drawings related to the embodiments of thedisclosure. Apparently, the described embodiments are just a part butnot all of the embodiments of the disclosure. Based on the describedembodiments herein, those skilled in the art can obtain otherembodiment(s), without any inventive work, which should be within thescope of the disclosure.

Unless otherwise defined, all the technical and scientific terms usedherein have the same meanings as commonly understood by one of ordinaryskill in the art to which the present disclosure belongs. The terms“first,” “second,” etc., which are used in the present disclosure, arenot intended to indicate any sequence, amount or importance, butdistinguish various components. Also, the terms “comprise,”“comprising,” “include,” “including,” etc., are intended to specify thatthe elements or the objects stated before these terms encompass theelements or the objects and equivalents thereof listed after theseterms, but do not preclude the other elements or objects. The phrases“connect”. “connected”, etc., are not intended to define a physicalconnection or mechanical connection, but may include an electricalconnection, directly or indirectly. “On.” “under,” “right,” “left” andthe like are only used to indicate relative position relationship, andwhen the position of the object which is described is changed, therelative position relationship may be changed accordingly.

Specific embodiments of the present disclosure are described in detailbelow with reference to the accompanying drawings. It should beunderstood that the specific embodiments described herein are intendedto describe and illustrate the present disclosure only and thus are notlimitative to the present disclosure.

At least some embodiments of the present disclosure provide a pixelcircuit. FIG. 1A is a schematic diagram of a pixel circuit provided bysome embodiments of the present disclosure; FIG. 1B is a schematicdiagram of another pixel circuit provided by some embodiments of thepresent disclosure; FIG. 2A is a schematic diagram of a circuitstructure of a pixel circuit provided by some embodiments of the presentdisclosure; FIG. 2B is a schematic diagram of a circuit structure ofanother pixel circuit provided by some embodiments of the presentdisclosure; FIG. 3A is a signal timing diagram of a pixel circuit duringoperation provided by some embodiments of the present disclosure; FIG.3B is another signal timing diagram of a pixel circuit during operationprovided by some embodiments of the present disclosure; FIG. 3C isfurther another signal timing diagram of a pixel circuit duringoperation provided by some embodiments of the present disclosure; FIG.4A is a diagram showing relationship of brightness and a voltage betweentwo terminals of a light emitting element provided by some embodimentsof the present disclosure; and FIG. 4B is a diagram showing relationshipof brightness and a voltage between two terminals of another lightemitting element provided by some embodiments of the present disclosure.

For example, as illustrated in FIG. 1A, in some embodiments, a pixelcircuit 10 includes a driving sub-circuit 100, a first data writingsub-circuit 110, a second data writing sub-circuit 120, and a storagesub-circuit 140. The pixel circuit 10 is configured to drive a lightemitting element OLED to emit light.

For example, the first data writing sub-circuit 110 is electricallyconnected to a first terminal of the storage sub-circuit 140. Undercontrol of a first data scanning signal, in a case where the first datawriting sub-circuit 110 is turned on, the first data writing sub-circuit110 is configured to write a first data voltage to the first terminal ofthe storage sub-circuit 140.

The second data writing sub-circuit 120 is electrically connected to asecond terminal of the storage sub-circuit 140. That is, the first datawriting sub-circuit 110 and the second data writing sub-circuit 120 arerespectively connected to two terminals of the storage sub-circuit 140.Under control of a second data scanning signal, in a case where thesecond data writing sub-circuit 120 is turned on, the second datawriting sub-circuit 120 is configured to write a second data voltage tothe second terminal of the storage sub-circuit 140, so as to control avoltage at the first terminal of the storage sub-circuit 140 based onthe second data voltage.

The first terminal of the storage sub-circuit 140 is furtherelectrically connected to a control terminal of the driving sub-circuit100; and the driving sub-circuit 100 is configured to drive the lightemitting element OLED to emit light under control of the voltage at thefirst terminal of the storage sub-circuit 140.

The pixel circuit provided by the embodiments of the present disclosurecan realize two operation modes, i.e., an operation mode of highbrightness and an operation mode of low brightness, while ensuring highcontrast ratio, and a structure thereof is simple and is easy to beimplemented. For example, the embodiments of the present disclosureprovide a Micro OLED driving scheme design for achieving high-voltagedriving by using a low-voltage wafer MOS process. By adding a seconddata writing sub-circuit in the pixel circuit, and by means of voltagejump, together with the cooperation of values of respective controlsignals, the two operation modes can be realized. Under the limitationof the established low-voltage MOS process (for example, 0.11 μm, 6Vprocess), the Micro OLED device can having high brightness and becompatible with high contrast ratio as well, within a specificvoltage-endurance range of the wafer, so that high-voltage driving ofthe light emitting element can be realized under low-voltage TFTprocess, thereby achieving high brightness and meanwhile ensuring highcontrast ratio.

For example, in some other embodiments, the pixel circuit 10 furtherincludes a reset sub-circuit 130 and a light emitting controlsub-circuit 150. As illustrated in FIG. 1B, the pixel circuit 10includes the driving sub-circuit 100, the first data writing sub-circuit110, the second data writing sub-circuit 120, the reset sub-circuit 130,the storage sub-circuit 140, and the light emitting control sub-circuit150.

For example, an output terminal of the first data writing sub-circuit110 is electrically connected to the first terminal of the storagesub-circuit 140, and an input terminal of the first data writingsub-circuit 110 and the output terminal of the first data writingsub-circuit 110 can be conductive under control of the first datascanning signal received by a control terminal of the first data writingsub-circuit 110.

For example, an output terminal of the second data writing sub-circuit120 is electrically connected to the second terminal of the storagesub-circuit 140, and an input terminal of the second data writingsub-circuit 120 and the output terminal of the second data writingsub-circuit 120 can be conductive under control of the second datascanning signal received by a control terminal of the second datawriting sub-circuit 120.

For example, the reset sub-circuit 130 is configured to reset the secondterminal of the storage sub-circuit 140 under control of a first resetcontrol signal, and to reset an anode of the light emitting element OLEDunder control of a second reset control signal.

For example, an input terminal of the reset sub-circuit 130 iselectrically connected to a first reference level signal terminal Vcom1and a second reference level signal terminal Vcom2, and a first outputterminal of the reset sub-circuit 130 is electrically connected to thesecond terminal of the storage sub-circuit 140, and a second outputterminal of the reset sub-circuit 130 is electrically connected to theanode of the light emitting element OLED. The input terminal of thereset sub-circuit 130 and the first output terminal of the resetsub-circuit 130 can be conductive under control of the first resetcontrol signal received by a control terminal of the reset sub-circuit130, and the input terminal of the reset sub-circuit 130 and the secondoutput terminal of the reset sub-circuit 130 can be conductive undercontrol of the second reset control signal received by the controlterminal of the reset sub-circuit 130. That is, the reset sub-circuit130 is configured to write a first reference level signal of the firstreference level signal terminal Vcom1 to the second terminal of thestorage sub-circuit 140 under control of the first reset control signal,so as to reset the second terminal of the storage sub-circuit 140, andthe reset sub-circuit 130 is further configured to write a secondreference level signal of the second reference level signal terminalVcom2 to the anode of the light emitting element OLED under control ofthe second reset control signal, so as to reset the anode of the lightemitting element OLED.

For example, the first terminal of the storage sub-circuit 140 iselectrically connected to the control terminal of the drivingsub-circuit 100, and the storage sub-circuit 140 is configured to storethe first data voltage written by the first data writing sub-circuit 110and the second data voltage written by the second data writingsub-circuit 120.

For example, the light emitting control sub-circuit 150 is configured toelectrically connect or disconnect the driving sub-circuit 100 and thelight emitting element OLED under control of a light emitting controlsignal. The light emitting control signal includes a first lightemitting control sub-signal and a second light emitting controlsub-signal.

As illustrated in FIG. 1A and FIG. 1B, a cathode of the light emittingelement OLED is electrically connected to a second level signal terminalVss. The light emitting control sub-circuit 150 is configured to allow apath to be formed between a first level signal terminal Vdd, a firstterminal of the driving sub-circuit 100, a second terminal of thedriving sub-circuit 100, the light emitting element OLED, and the secondlevel signal terminal Vss upon receiving the first light emittingcontrol sub-signal, and the light emitting control sub-circuit 150 isfurther configured to disconnect the path between the first level signalterminal Vdd, the first terminal of the driving sub-circuit 100, thesecond terminal of the driving sub-circuit 100, the light emitting diodeOLED, and the second level signal terminal Vss upon receiving the secondlight emitting control sub-signal.

For example, the light emitting element OLED can be a light emittingdiode, etc. The light emitting diode can be an organic light emittingdiode (OLED) or a quantum dot light emitting diode (QLED), etc. Thelight emitting element OLED is configured to receive a light emittingsignal (e.g., may be a current signal) during operation, and to emitlight of an intensity corresponding to the light emitting signal.

For example, one of the first level signal terminal Vdd and the secondlevel signal terminal Vss is a high level signal terminal, and the otheris a low level signal terminal. In the embodiments illustrated in FIG.1A and FIG. 1B, the first level signal terminal Vdd is a voltage sourcefor outputting a constant positive voltage; and the second level signalterminal Vss can be a voltage source for outputting a constant negativevoltage, or can be grounded, or the like.

For example, during the operation process of the pixel circuit 10, thesignal outputted by the second level signal terminal Vss remainsunchanged.

The pixel circuit provided by the present disclosure includes, in total,two data writing sub-circuits, i.e., the first data writing sub-circuit110 and the second data writing sub-circuit 120.

The pixel circuit 10 can be applied in a display panel, such as anAMOLED display panel or the like. The final display brightness and imagecontrast ratio of the display panel are related to a voltage differenceV_(EL) between the anode and the cathode of the light emitting elementOLED. The light emitting element OLED has two operation modes. In a casewhere the voltage difference V_(EL) between the anode and the cathode ofthe light emitting element OLED is within a first range. Mode One (i.e.,a first operation mode) of high brightness can be realized, and in acase where the voltage difference V_(EL) between the anode and thecathode of the light emitting element OLED is within a second range,Mode Two (i.e., a second operation mode) of high contrast ratio can berealized.

The operation mode of a specific light emitting element is illustratedin FIG. 4A, and the operation mode of another specific light emittingelement is illustrated in FIG. 4B. In some examples, as illustrated inFIG. 4A, in a case where the voltage difference V_(EL) between the anodeand the cathode of the light emitting element is within 4.3V to 5.4V,Mode Two of high contrast ratio can be realized; and in a case where thevoltage difference V_(EL) between the anode and the cathode of the lightemitting element is within 5.1V to 6.1V, Mode One of high brightness canbe realized. That is, the first range is 4.3V to 5.4V, and the secondrange is 5.1V to 6.1V. The present disclosure is not limited thereto.For example, in some other examples, as illustrated in FIG. 4B, in acase where the voltage difference V_(EL) between the anode and thecathode of the light emitting element is within 4.5V to 7.0V, Mode Twoof high contrast ratio can be realized; and in a case where the voltagedifference V_(EL) between the anode and the cathode of the lightemitting element is within 6.2V to 8.5V, Mode One of high brightness canbe realized. That is, the first range is 4.5V to 7.0V, and the secondrange is 6.2V to 8.5V.

In a case where brightness of the environment in which the display panelincluding the pixel circuit is located is high, and the display panel isrequired to realize a display effect of high brightness and highcontrast ratio, the second data scanning signal is provided to thecontrol terminal of the second data writing sub-circuit 120, and thesecond data voltage is provided to the input terminal of the second datawriting sub-circuit 120, so as to boost the voltage at the firstterminal of the storage sub-circuit 140, and thus, the voltagedifference between two terminals of the light emitting element OLED canbe increased, thereby ensuring the display effect of high brightness andhigh contrast ratio.

In a case where brightness of the environment in which the display panelincluding the pixel circuit is located is low, and the display panel isrequired to realize a display effect of low brightness and high contrastratio, inputting the second data voltage to the storage sub-circuit 140via the second data writing sub-circuit 120 is stopped, or the firstdata voltage is provided to the storage sub-circuit 140 via the seconddata writing sub-circuit 120, so as to ensure a small voltage differencebetween two terminals of the light emitting element OLED, therebyrealizing the display effect of low brightness and high contrast ratio.

It can be seen that when the two different operation modes areimplemented by using the pixel circuit 10 provided by the presentdisclosure, it is not necessary to provide two low-level signalterminals, nor to provide a complicated voltage switching circuit, andthe pixel circuit 10 is easy to be implemented.

It should be noted that the transistors used in the embodiments of thepresent disclosure can be thin film transistors or field effecttransistors or other switching elements having the same characteristics,and the thin film transistors can include oxide semiconductor thin filmtransistors, amorphous silicon thin film transistors or poly-siliconthin film transistors, etc. The source electrode and the drain electrodeof the transistor can be symmetrical in structure, so the sourceelectrode and the drain electrode of the transistor can be physicallyindistinguishable. In the embodiments of the present disclosure, inorder to distinguish the electrodes of the transistor, except for thegate electrode serving as a control electrode, one of the restelectrodes is directly described as a first electrode, while the otheras a second electrode. Therefore, in the embodiments of the presentdisclosure, the first electrode and the second electrode of all or partof the transistors are interchangeable as needed. For example, in someembodiments, the driving transistor used in the pixel circuit 10provided by the present disclosure is a silicon-based transistor. Forthe silicon-based transistor, the problem of threshold voltage shift isnot likely to occur, and thus, it is not necessary to provide athreshold compensation sub-circuit in the pixel circuit 10 provided bythe present disclosure, either. However, the present disclosure is notlimited thereto, and the threshold compensation sub-circuit can also beprovided in the pixel circuit 10 provided by the present disclosure.

For example, according to the characteristics of the transistors, thetransistors can be divided into N-type transistors and P-typetransistors. For the sake of clarity, the embodiments of the presentdisclosure take the case that the transistors P1-P3 and the drivingtransistor DTFT are P-type transistors (for example, P-type MOStransistors), and the transistors N1-N3 are N-type transistors, as anexample, to illustrate the technical solutions of the presentdisclosure. However, the transistors of the embodiments of the presentdisclosure are not limited to the above case, and those skilled in theart can also set the types of the transistors in the present disclosureas needed.

In the present disclosure, the reset sub-circuit 130 is configured toreset the storage sub-circuit 140 and the anode of the light emittingelement OLED, and the light emitting control sub-circuit 150 isconfigured to prevent the light emitting element OLED from emittinglight before the light emitting phase.

FIG. 2A is a schematic diagram of a circuit structure of the pixelcircuit illustrated in FIG. 1B, and the pixel circuit of the presentdisclosure is described in detail below with reference to FIG. 2A.

For example, as illustrated in FIG. 2A, the driving sub-circuit 100includes a driving transistor DTFT. A first electrode of the drivingtransistor DTFT is electrically connected to the light emitting controlsub-circuit 150, a second electrode of the driving transistor DTFT iselectrically connected to the anode of the light emitting element OLED,the control terminal of the driving sub-circuit 100 includes a gateelectrode of the driving transistor DTFT, and the gate electrode of thedriving transistor DTFT is electrically connected to the first terminalof the storage sub-circuit 140.

For example, the cathode of the light emitting element OLED iselectrically connected to the second level signal terminal Vss.

For example, the control terminal of the first data writing sub-circuit110 is electrically connected to a first gate line, so as to receive thefirst data scanning signal. In some embodiments, the control terminal ofthe first data writing sub-circuit 110 includes a first controlsub-terminal and a second control sub-terminal, the first data scanningsignal includes a first data scanning sub-signal and a second datascanning sub-signal, the first control sub-terminal is configured toreceive the first data scanning sub-signal, and the second controlsub-terminal is configured to receive the second data scanningsub-signal.

For example, in some examples, the first control sub-terminal is anN-type control terminal and the second control sub-terminal is a P-typecontrol terminal. The first data scanning sub-signal is an N-type datascanning signal, and the second data scanning sub-signal is a P-typedata scanning signal.

For example, as illustrated in FIG. 2A, the first data writingsub-circuit 110 includes an N-type data writing transistor N1 and aP-type data writing transistor P1. The input terminal of the first datawriting sub-circuit 110 includes a first electrode of the N-type datawriting transistor N1 and a first electrode of the P-type data writingtransistor P1, the output terminal of the first data writing sub-circuit110 includes a second electrode of the N-type data writing transistor N1and a second electrode of the P-type data writing transistor P1, and thecontrol terminal of the first data writing sub-circuit 110 includes agate electrode of the N-type data writing transistor N1 and a gateelectrode of the P-type data writing transistor P1.

For example, the first electrode of the N-type data writing transistorN1 and the first electrode of the P-type data writing transistor P1 areboth configured to receive the first data voltage. For example, thefirst electrode of the N-type data writing transistor N1 and the firstelectrode of the P-type data writing transistor P1 are both electricallyconnected to a first data signal line D1 to receive the first datavoltage. The second electrode of the N-type data writing transistor N1and the second electrode of the P-type data writing transistor P1 areboth electrically connected to the first terminal of the storagesub-circuit 140. The first control sub-terminal includes the gateelectrode of the N-type data writing transistor N1, and the secondcontrol sub-terminal includes the gate electrode of the P-type datawriting transistor P1, that is, the gate electrode of the N-type datawriting transistor N1 is configured to receive the first data scanningsub-signal, and the gate electrode of the P-type data writing transistorP1 is configured to receive the second data scanning sub-signal.

For example, the first gate line includes a first gate sub-line G1 and asecond gate sub-line G2, the first gate sub-line G1 is configured tooutput the first data scanning sub-signal, and the second gate sub-lineG2 is configured to output the second data scanning sub-signal.Therefore, as illustrated in FIG. 2A, the gate electrode of the N-typedata writing transistor N1 is electrically connected to the first gatesub-line G1 to receive the first data scanning sub-signal, and the gateelectrode of the P-type data writing transistor P1 is electricallyconnected to the second gate sub-line G2 to receive the second datascanning sub-signal.

For example, the first data writing sub-circuit 110 adopts twotransistors of different types, so that the voltage range of the datavoltage being written can be increased. The N-type data writingtransistor N1 corresponds to the first data voltage of high level, andthe P-type data writing transistor P1 corresponds to the first datavoltage of low level.

For example, as illustrated in FIG. 2A, the second data writingsub-circuit 120 includes a first data writing transistor P3. The inputterminal of the second data writing sub-circuit 120 includes a firstelectrode of the first data writing transistor P3, and the outputterminal of the second data writing sub-circuit 120 includes a secondelectrode of the first data writing transistor P3, and the controlterminal of the data writing sub-circuit 120 includes a gate electrodeof the first data writing transistor P3.

For example, the first data writing transistor P3 can be, for example, aP-type transistor, but the present disclosure is not limited thereto,and the first data writing transistor P3 can also be an N-typetransistor.

For example, the gate electrode of the first data writing transistor P3is electrically connected to a second gate line G3 to receive the seconddata scanning signal, and the first electrode of the first data writingtransistor P3 is electrically connected to a second data line D2 toreceive the second data voltage, and the second electrode of the firstdata writing transistor P3 is electrically connected to the secondterminal of the storage sub-circuit 140.

For example, in a case where the second data scanning signal is at afirst level, the first data writing transistor P3 is turned on, and in acase where the second data scanning signal is at a second level, thefirst data writing transistor P3 is turned off, and the first level isopposite to the second level. For example, in a case where the firstdata writing transistor P3 is a P-type transistor, the first level is alow level and the second level is a high level; and in a case where thefirst data writing transistor P3 is an N-type transistor, the firstlevel is a high level and the second level is a low level.

For example, as illustrated in FIG. 2A, the storage sub-circuit 140includes a storage capacitor C. The first terminal of the storagesub-circuit 140 includes a first terminal of the storage capacitor C,and the second terminal of the storage sub-circuit 140 includes a secondterminal of the storage capacitor C. That is, the first terminal of thestorage capacitor C is electrically connected to the second electrode ofthe N-type data writing transistor N1 and the second electrode of theP-type data writing transistor P1, and the second terminal of thestorage capacitor C is electrically connected to the second electrode ofthe first data writing transistor P3.

For example, in a case where the first data writing transistor P3 writesthe second data voltage to the second terminal of the storage capacitorC, the voltage at the first terminal of the storage capacitor C changescorrespondingly due to the bootstrap effect of the storage capacitor C,and a change amount can be the second data voltage, thereby pulling upor pulling down the voltage at the first terminal of the storagecapacitor C. For example, in a case where the second data voltage is apositive voltage, the voltage at the first terminal of the storagecapacitor C is pulled up; and in a case where the second data voltage isa negative voltage, the voltage at the first terminal of the storagecapacitor C is pulled down. It should be noted that before the firstdata writing transistor P3 writes the second data voltage to the secondterminal of the storage capacitor C, the voltage at the second terminalof the storage capacitor C can be 0V.

For example, as illustrated in FIG. 2A, the reset sub-circuit 130includes a first reset transistor N2 and a second reset transistor N3.The input terminal of the reset sub-circuit 130 includes a firstelectrode of the first reset transistor N2 and a first electrode of thesecond reset transistor N3, the first output terminal of the resetsub-circuit 130 includes a second electrode of the first resettransistor N2, and the second output terminal of the reset sub-circuit130 includes a second electrode of the second reset transistor N3.

For example, as illustrated in FIG. 2A, a gate electrode of the firstreset transistor N2 is connected to a first reset control signal lineRS1 to receive the first reset control signal, the first electrode ofthe first reset transistor N2 is electrically connected to the firstreference level signal terminal Vcom1 to receive the first referencelevel signal, and the second electrode of the first reset transistor N2is electrically connected to the second terminal of the storagesub-circuit 140, that is, the second electrode of the first resettransistor N2 is electrically connected to the second terminal of thestorage capacitor C. In a case where the first reset transistor N2 isturned on under control of the first reset control signal, the firstreference level signal of the first reference level signal terminalVcom1 is transmitted to the second terminal of the storage capacitor Cvia the first reset transistor N2, so as to reset the second terminal ofthe storage capacitor C.

For example, as illustrated in FIG. 2A, a gate electrode of the secondreset transistor N3 is connected to a second reset control signal lineRS2 to receive the second reset control signal, the first electrode ofthe second reset transistor N3 is electrically connected to the secondreference level signal terminal Vcom2 to receive the second referencelevel signal, and the second electrode of the second reset transistor N3is electrically connected to the anode of the light emitting elementOLED. In a case where the second reset transistor N3 is turned on undercontrol of the second reset control signal, the second reference levelsignal of the second reference level signal terminal Vcom2 istransmitted to the anode of the light emitting element OLED via thesecond reset transistor N3, so as to reset the anode of the lightemitting element OLED.

For example, in some embodiments, as illustrated in FIG. 2A, the firstreset control signal and the second reset control signal can bedifferent signals. Alternatively, in some other embodiments, asillustrated in FIG. 2B, the first reset control signal and the secondreset control signal are identical, i.e., the two are a same signal, sothat the first reset control signal line RS1 or the second reset controlsignal line RS2 may be omitted. That is, in a case where only the firstreset control signal line RS1 is provided, the gate electrode of thefirst reset transistor N2 and the gate electrode of the second resettransistor N3 can both be electrically connected to the first resetcontrol signal line RS1; and in a case where only the second controlsignal line RS2 is provided, the gate electrode of the first resettransistor N2 and the gate electrode of the second reset transistor N3can both be electrically connected to the second reset control signalline RS2.

For example, as illustrated in FIG. 2A, the first reference level signaland the second reference level signal can be different, but theembodiments of the present disclosure are not limited thereto. Asillustrated in FIG. 2B, in some other embodiments, the first referencelevel signal and the second reference level signal can be identical. Ina case where the first reference level signal and the second referencelevel signal are identical, only the first reference level signalterminal Vcom1 or only the second reference level signal terminal Vcom2may be provided. That is, in a case where only the first reference levelsignal terminal Vcom1 is provided, the first electrode of the firstreset transistor N2 and the first electrode of the second resettransistor N3 can both be electrically connected to the first referencelevel signal terminal Vcom1; and in a case where only the secondreference level signal terminal Vcom2 is provided, the first electrodeof the first reset transistor N2 and the first electrode of the secondreset transistor N3 can both be electrically connected to the secondreference level signal terminal Vcom2.

For example, the first reference level signal and the second referencelevel signal can both be set to 0V.

For example, as illustrated in FIG. 2A, the light emitting controlsub-circuit 150 includes a light emitting control transistor P2. A gateelectrode of the light emitting control transistor P2 is configured toreceive the light emitting control signal, a first electrode of thelight emitting control transistor P2 is electrically connected to thefirst level signal terminal Vdd, and a second electrode of the lightemitting control transistor P2 is electrically connected to the drivingsub-circuit 100. For example, a gate electrode of the light emittingcontrol transistor P2 is connected to a light emitting control signalline EM to receive the light emitting control signal, and the secondelectrode of the light emitting control transistor P2 is electricallyconnected to the first electrode of the driving transistor DTFT.

The operation principle of the pixel circuit of the present disclosureis described in detail below with reference to the signal timingdiagrams provided in FIG. 3A, FIG. 3B, and FIG. 3C. In a case where thedisplay panel including the pixel circuit operates in the firstoperation mode of high contrast ratio and high brightness, an operationperiod of the pixel circuit includes a reset phase T1, a charging phaseT2, a voltage jump phase T3, and a light emitting phase T4.

It should be noted that, in the following description of the presentdisclosure, the case that the first reset control signal and the secondreset control signal are a same signal, and the first reference levelsignal and the second reference level signal are both set to 0V, istaken as an example. In the examples illustrated in FIG. 3A and FIG. 3B,the driving transistor DTFT is an N-type transistor, while in theexample illustrated in FIG. 3C, the driving transistor DTFT is a P-typetransistor.

For example, as illustrated in FIG. 3A and FIG. 3B, in a case where thedriving transistor DTFT is an N-type transistor, the operation principleof the pixel circuit is as follows.

In the reset phase T1, the first reset control signal is provided to thefirst control terminal of the reset sub-circuit 130 through the firstreset control signal line RS1, so as to electrically connect the inputterminal of the reset sub-circuit 130 and the first output terminal ofthe reset sub-circuit 130, and further, to write the first referencelevel signal provided by the first reference level signal terminal Vcom1to the second terminal of the storage sub-circuit 140, thereby resettingthe second terminal of the storage sub-circuit 140 to facilitate writingthe second data voltage in a subsequent phase. Moreover, in this resetphase T1, the second reset control signal is provided to the secondcontrol terminal of the reset sub-circuit 130 through the second resetcontrol signal line RS2, so as to electrically connect the inputterminal of the reset sub-circuit 130 and the second output terminal ofthe reset sub-circuit 130, and thus, the second reference level signalprovided by the second reference level signal terminal Vcom2 can bewritten into the anode of the light emitting element OLED to reset theanode of the light emitting element OLED.

In the charging phase T2, the first data scanning sub-signal and thesecond data scanning sub-signal are provided to the control terminal ofthe first data writing sub-circuit 110 through the first gate sub-lineG1 and the second gate sub-line G2, and the first data voltage isprovided to the input terminal of the first data writing sub-circuit 110through the first data line D1, so as to electrically connect the inputterminal of the first data writing sub-circuit 110 and the outputterminal of the first data writing sub-circuit 110, thereby writing thefirst data voltage to the first terminal of the storage sub-circuit 140and enabling the gate voltage of the driving transistor DTFT to reach afirst voltage V1.

For example, in the example illustrated in FIG. 3A, in the chargingphase T2, the first data scanning sub-signal provided by the first gatesub-line G1 is at a high level, and the second data scanning sub-signalprovided by the second gate sub-line G2 is at a low level, so that boththe N-type data writing transistor and the P-type data writingtransistor in the first data writing sub-circuit 110 are turned on.However, the embodiments of the present disclosure are not limitedthereto. In some examples, in the charging phase T2, one of the N-typedata writing transistor and the P-type data writing transistor is turnedon, and the other is turned off. For example, in a case where the firstdata voltage is a positive voltage, the N-type data writing transistorcan be turned on, and the P-type data writing transistor can be turnedoff; and in a case where the first data voltage is a negative voltage,the N-type data writing transistor can be turned off, and the P-typedata writing transistor can be turned on.

In the voltage jump phase T3, the second data scanning signal isprovided to the control terminal of the second data writing sub-circuit120 through the second gate line G3, so as to electrically connect theinput terminal of the second data writing sub-circuit 120 and the outputterminal of the second data writing sub-circuit 120, thereby storing thesecond data voltage written by the input terminal of the second datawriting sub-circuit 120 into the second terminal of the storagesub-circuit 140. In the voltage jump phase T3, due to the bootstrapeffect of the storage capacitor C, in a case where the voltage at thesecond terminal of the storage sub-circuit 140 (i.e., the secondterminal of the storage capacitor C) jumps from the first referencelevel signal in the charging phase T2, i.e., 0V, to the second datavoltage in the voltage jump phase T3, the voltage at the first terminalof the storage sub-circuit 140, that is, the gate voltage of the drivingtransistor DTFT jumps from the first voltage V1 in the charging phase T2to a second voltage V2 in the voltage jump phase T3. The voltagethreshold of a transistor is a fixed threshold (that is, the voltagedifference between any two of the three electrodes of the transistordoes not exceed the above fixed threshold, for example, 6V), so thecontrol signals of the remaining transistors should jump accordingly toensure the normal operation of each transistor. Specifically, the levelof the first data scanning sub-signal provided to the control terminalof the first data writing sub-circuit through the first gate sub-line G1is higher than the level of the first data scanning sub-signal in thecharging phase T2, and the level of the second data scanning sub-signalprovided to the control terminal of the first data writing sub-circuitthrough the second gate sub-line G2 is higher than the level of thesecond data scanning sub-signal in the charging phase T2, so that thetransistor of the first data writing sub-circuit can be ensured tooperate within a range allowed by the voltage threshold.

For example, as illustrated in FIG. 3A and FIG. 3B, in the reset phaseT1, the level of the first data scanning sub-signal is a first datalevel, the level of the second data scanning sub-signal is a second datalevel, the level of the first reset control signal is a first resetlevel, and the level of the second reset control signal is the firstreset level. In the charging phase T2, the level of the first datascanning sub-signal is a third data level, the level of the second datascanning sub-signal is a fourth data level, the level of the first resetcontrol signal is a second reset level, and the level of the secondreset control signal is the second reset level. In the voltage jumpphase T3, the level of the first data scanning sub-signal is a fifthdata level, the level of the second data scanning sub-signal is a sixthdata level, the level of the first reset control signal is a third resetlevel, and the level of the second reset control signal is the thirdreset level. The first data level is lower than the third data level,the third data level is lower than the fifth data level, the second datalevel is higher than the fourth data level, the sixth data level ishigher than the second data level, the first reset level is higher thanthe second reset level, and the first reset level is equal to the thirdreset level. That is, in the voltage jump phase T3, the level of thefirst data scanning sub-signal jumps from the first data level to thefifth data level, the level of the second data scanning sub-signal jumpsfrom the second data level to the sixth data level, and the levels ofthe first reset control signal and the second reset control signal jumpfrom the second reset level to the third reset level.

In the light emitting phase T4, the gate voltage of the drivingtransistor DTFT is the second voltage V2 mentioned above, therefore, byproviding the light emitting control signal to the light emittingcontrol sub-circuit 150 through the light emitting control signal lineEM, the first level signal terminal Vdd, the first electrode of thedriving transistor DTFT, the second electrode of the driving transistorDTFT, the light emitting diode OLED and the second level signal terminalVss can form a path, so as to drive the light emitting element OLED toemit light.

For example, as illustrated in FIG. 3A and FIG. 3B, in some examples,both in the reset phase T1 and in the charging phase T2, the level ofthe light emitting control signal is a first light emitting controllevel; in the voltage jump phase T3, the level of the light emittingcontrol signal is a second light emitting control level; and in thelight emitting phase T4, the level of the light emitting control signalis a third light emitting control level. The first light emittingcontrol level is lower than the second light emitting control level, andthe first light emitting control level is equal to the third lightemitting control level. That is, in the voltage jump phase T3, the levelof the light emitting control signal jumps from the first light emittingcontrol level to the second light emitting control level; and in thelight emitting phase T4, the level of the light emitting control signalchanges from the second light emitting control level to the third lightemitting control level.

For example, as illustrated in FIG. 3A, in some examples, in the lightemitting phase T4, the level of the first data scanning sub-signal is aseventh data level, the seventh data level is lower than the fifth datalevel, and the seventh data level can be equal to the third data level.That is, the level of the first data scanning sub-signal jumps from thefifth data level to the third data level; and the level of the seconddata scanning sub-signal maintains at the sixth data level, and thelevels of the first reset control signal and the second reset controlsignal also maintain at the third reset level, that is, the level of thefirst reset control signal and the level of the second data scanningsub-signal do not jump.

For another example, as illustrated in FIG. 3B, in some other examples,in the light emitting phase T4, the level of the first data scanningsub-signal maintains at the fifth data level; and the level of thesecond data scanning sub-signal maintains at the sixth data level, andthe levels of the first reset control signal and the second resetcontrol signal also maintain at the third reset level, that is, thelevels of the first reset control signal and the second reset controlsignal, the level of the first data scanning sub-signal, and the levelof the second data scanning sub-signal do not jump.

For example, as illustrated in FIG. 3C, in a case where the drivingtransistor DTFT is a P-type transistor, the operation principle of thepixel circuit is similar to that in the case where the drivingtransistor DTFT is an N-type transistor, except that the levels of therespective control signals are different.

For example, in the reset phase T1, the level of the first data scanningsub-signal is a first data level, the level of the second data scanningsub-signal is a second data level, the level of the first reset controlsignal is a first reset level, the level of the second reset controlsignal is the first reset level, and the level of the light emittingcontrol signal is a first light emitting control level; in the chargingphase T2, the level of the first data scanning sub-signal is a thirddata level, the level of the second data scanning sub-signal is a fourthdata level, the level of the first reset control signal is a secondreset level, the level of the second reset control signal is the secondreset level, and the level of the light emitting control signal is thefirst light emitting control level; in the voltage jump phase T3, thelevel of the first data scanning sub-signal is a fifth data level, thelevel of the second data scanning sub-signal is a sixth data level, thelevel of the first reset control signal is a third reset level, thelevel of the second reset control signal is the third reset level, andthe level of the light emitting control signal is a second lightemitting control level; and in the light emitting phase T4, the level ofthe first data scanning sub-signal is the fifth data level, the level ofthe second data scanning sub-signal is the sixth data level, the levelof the first reset control signal is the third reset level, the level ofthe second reset control signal is the third reset level, and the levelof the light emitting control signal is a third light emitting controllevel.

For example, the first data level is lower than the third data level,the fifth data level is lower than the first data level, the second datalevel is higher than the fourth data level, the fourth data level ishigher than the sixth data level, the first reset level is higher thanthe second reset level, the second reset level is higher than the thirdreset level, the first light emitting control level is higher than thesecond light emitting control level, and the second light emittingcontrol level is higher than the third light emitting control level.That is, in the voltage jump phase T3, the level of the first datascanning sub-signal jumps from the first data level to the fifth datalevel, the level of the second data scanning sub-signal jumps from thesecond data level to the sixth data level, the levels of the first resetcontrol signal and the second reset control signal jump from the secondreset level to the third reset level, and the level of the lightemitting control signal jumps from the first light emitting controllevel to the second light emitting control level. In the light emittingphase T4, the third light emitting control level is lower than thesecond light emitting control level, so as to ensure that the lightemitting control transistor P2 is turned on in the light emitting phaseT4.

For example, in the reset phase T1, the charging phase T2 and the lightemitting phase T4, the second data scanning signal is at a second level;and in the voltage jump phase T3, the second data scanning signal is ata first level. In the examples illustrated in FIGS. 3A-3C, the secondlevel is a high level, and the first level is a low level.

According to the relationship between the gate voltage of thesilicon-based driving transistor DTFT, the threshold voltage of thedriving transistor DTFT, and the voltage difference V_(EL) between theanode and cathode of the light emitting element OLED, the voltagedifference V_(EL) between the anode and cathode of the light emittingelement OLED can be calculated.

For example, in a case where the gate voltage of the driving transistorDTFT is between 1V and 5V, the threshold voltage of the drivingtransistor DTFT is 1V, and the voltage provided by the second levelsignal terminal Vss is −3V, the voltage of the cathode of the lightemitting element OLED is −3V, and a source voltage of the drivingtransistor DTFT is between 0V and 4V, that is, the voltage of the anodeof the light emitting element OLED is between 0V and 4V. Therefore, thevoltage difference V_(EL) between the anode and the cathode of the lightemitting element OLED is 3V˜7V. It can be seen from FIG. 4B that thelight emitting element OLED operates in Mode Two, which can realize lowbrightness and high contrast ratio.

It should be noted that in a case where the display device is requiredto display with high brightness, in the voltage jump phase T3, thesecond data scanning signal is provided to the control terminal of thesecond data writing sub-circuit 120, and the second data voltage isprovided to the input terminal of the second data writing sub-circuit120, and the second data voltage can be higher than the first datavoltage. In this case, the gate voltage of the driving transistor DTFTcan be between 5V and 9V, so that the source voltage of the drivingtransistor DTFT is between 4V and 8V, that is, the voltage of the anodeof the light emitting element OLED is between 4V and 8V. Therefore, thevoltage difference V_(EL) between the anode and the cathode of the lightemitting element OLED is 7V˜11V, and the light emitting element OLEDoperates in Mode One, which can realize high brightness and highcontrast ratio.

In the present disclosure, the specific structure of the first datawriting sub-circuit 110 is not particularly limited. In an embodiment,the control terminal of the first data writing sub-circuit 110 includesan N-type control terminal (i.e., the first control sub-terminal) and aP-type control terminal (i.e., the second control sub-terminal).Accordingly, the first data scanning signal includes a first N-type datascanning signal and a first P-type data scanning signal. In the chargingphase T2, the first N-type data scanning signal is provided to theN-type control terminal of the first data writing sub-circuit 110, andthe first P-type data scanning signal is provided to the P-type controlterminal of the first data writing sub-circuit 110.

For example, as illustrated in FIG. 2B, the first data writingsub-circuit 110 includes an N-type data writing transistor N1 and aP-type data writing transistor P1, a first electrode of the N-type datawriting transistor N1 is electrically connected to a first electrode ofthe P-type data writing transistor P1 to form the input terminal of thefirst data writing sub-circuit 110, and a second electrode of the N-typedata writing transistor N1 is electrically connected to a secondelectrode of the P-type data writing transistor P1 to form the outputterminal of the first data writing sub-circuit 110. A gate electrode ofthe N-type data writing transistor N1 serves as the N-type controlterminal, and a gate electrode of the P-type data writing transistor P1serves as the P-type control terminal. It can be seen that the N-typedata writing transistor N1 and the P-type data writing transistor P1form a transmission gate.

The first electrode of the N-type data writing transistor N1 and thesecond electrode of the N-type data writing transistor N1 can beelectrically connected in a case where the gate electrode of the N-typedata writing transistor N1 receives the first N-type data scanningsignal, and the first electrode of the N-type data writing transistor N1and the second electrode of the N-type data writing transistor N1 can bedisconnected in a case where the gate electrode of the N-type datawriting transistor N1 receives a third N-type data scanning signal. Thefirst data scanning sub-signal includes the first N-type data scanningsignal and the third N-type data scanning signal, the first N-type datascanning signal is a high-level signal, and the third N-type datascanning signal is a low-level signal.

The first electrode of the P-type data writing transistor P1 and thesecond electrode of the P-type data writing transistor P1 can beelectrically connected in a case where the gate electrode of the P-typedata writing transistor P1 receives the first P-type data scanningsignal, and the first electrode of the P-type data writing transistor P1and the second electrode of the P-type data writing transistor P1 can bedisconnected in a case where the gate electrode of the P-type datawriting transistor P1 receives a third P-type data scanning signal. Thesecond data scanning sub-signal includes the first P-type data scanningsignal and the third P-type data scanning signal, the first P-type datascanning signal is a low-level signal, and the third P-type datascanning signal is a high-level signal.

The first data writing sub-circuit 110 is formed in the form of atransmission gate which includes the P-type data writing transistor andthe N-type data writing transistor, thereby increasing the range of thedata voltage allowed to be inputted by the first data writingsub-circuit 110. Specifically, the N-type data writing transistor N1 canallow a data voltage having a high voltage value to be inputted, and theP-type data writing transistor P1 can allow a data voltage having a lowvoltage value to be inputted.

In the present disclosure, the specific structure of the resetsub-circuit 130 is not particularly limited. In the specific embodimentillustrated in FIG. 2B, the reset sub-circuit 130 includes a first resettransistor N2 and a second reset transistor N3, and the first resettransistor N2 is an N-type transistor. A gate electrode of the firstreset transistor N2 and a gate electrode of the second reset transistorN3 both receive the first reset control signal, that is, the first resettransistor N2 and the second reset transistor N3 are controlled by asame first reset control signal.

As illustrated in FIG. 2B, the gate electrode of the first resettransistor N2 serves as the control terminal of the reset sub-circuit130, a first electrode of the first reset transistor N2 serves as theinput terminal of the reset sub-circuit 130, and a second electrode ofthe first reset transistor N2 serves as the first output terminal of thereset sub-circuit 130. The first electrode of the first reset transistorN2 and the second electrode of the first reset transistor N2 can beelectrically connected in a case where the gate electrode of the firstreset transistor N2 receives a first reset control sub-signal, and thefirst electrode of the first reset transistor N2 and the secondelectrode of the first reset transistor N2 can be disconnected in a casewhere the gate electrode of the first reset transistor N2 receives asecond reset control sub-signal. The first reset control signal includesthe first reset control sub-signal and the second reset controlsub-signal, and the first reset control sub-signal and the second resetcontrol sub-signal are in opposite phases. The first electrode of thefirst reset transistor N2 is electrically connected to the firstreference level signal terminal Vcom1, and therefore, the secondterminal of the storage sub-circuit 130 can be reset by using the firstreset transistor N2.

The gate electrode of the second reset transistor N3 is electricallyconnected to the gate electrode of the first reset transistor N2, afirst electrode of the second reset transistor N3 is electricallyconnected to the first electrode of the first reset transistor N2, and asecond electrode of the second reset transistor N3 serves as the secondoutput terminal of the reset sub-circuit 130. The first electrode of thesecond reset transistor N3 and the second electrode of the second resettransistor N3 can be electrically connected in a case where the gateelectrode of the second reset transistor N3 receives the first resetcontrol sub-signal, and the first electrode of the second resettransistor N3 and the second electrode of the second reset transistor N3can be disconnected in a case where the gate electrode of the secondreset transistor N3 receives the second reset control sub-signal.

The first electrode of the second reset transistor N3 is electricallyconnected to the first reference level signal terminal Vcom1, andtherefore, the anode of the light emitting element OLED can be reset byusing the second reset transistor N3.

In the present disclosure, the type of the second reset transistor N3 isnot particularly limited. For example, in the specific embodimentillustrated in FIG. 2B, the second reset transistor N3 is an N-typetransistor.

In the present disclosure, the specific structure of the second datawriting sub-circuit 120 is not particularly limited. For example, asillustrated in FIG. 2B, the second data writing sub-circuit 120 includesa first data writing transistor P3. A gate electrode of the first datawriting transistor P3 serves as the control terminal of the second datawriting sub-circuit 120, a first electrode of first data writingtransistor P3 serves as the input terminal of the second data writingsub-circuit 120, and a second electrode of first data writing transistorP3 serves as the output terminal of the second data writing sub-circuit120.

The first electrode of the first data writing transistor P3 and thesecond electrode of the first data writing transistor P3 can beelectrically connected in a case where the gate electrode of the firstdata writing transistor P3 receives a third data scanning sub-signal,and the first electrode of the first data writing transistor P3 and thesecond electrode of the first data writing transistor P3 can bedisconnected in a case where the gate electrode of the first datawriting transistor P3 receives a fourth data scanning sub-signal. Forexample, the second data scanning signal includes the third datascanning sub-signal and the fourth data scanning sub-signal, and thethird data scanning sub-signal and the fourth data scanning sub-signalare in opposite phases.

For example, the third data scanning sub-signal is a signal when thesecond data scanning signal is at the first level, and the fourth datascanning sub-signal is a signal when the second data scanning signal isat the second level.

For example, as illustrated in FIG. 2B, the first data writingtransistor P3 is a P-type transistor. In this case, the third datascanning sub-signal is a low-level signal, and the fourth data scanningsub-signal is a high-level signal. Of course, the present disclosure isnot limited to this case, and for example, the first data writingtransistor P3 can also be set as an N-type transistor.

In the present disclosure, the specific structure of the light emittingcontrol sub-circuit 150 is not particularly limited. In order tosimplify the structure of the light emitting control sub-circuit 150,for example, the light emitting control sub-circuit 150 includes a lightemitting control transistor P2.

For example, a gate electrode of the light emitting control transistorP2 serves as the control terminal of the light emitting controlsub-circuit 150, a first electrode of the light emitting controltransistor P2 is electrically connected to the first level signalterminal Vdd, and a second electrode of the light emitting controltransistor P2 is electrically connected to the first electrode of thedriving transistor DTFT.

The first electrode of the light emitting control transistor P2 and thesecond electrode of the light emitting control transistor P2 can beelectrically connected in a case where the gate electrode of the lightemitting control transistor P2 receives a first light emitting controlsub-signal, and the first electrode of the light emitting controltransistor P2 and the second electrode of the light emitting controltransistor P2 can be disconnected in a case where the gate electrode ofthe light emitting control transistor P2 receives a second lightemitting control sub-signal. For example, the light emitting controlsignal includes the first light emitting control sub-signal and thesecond light emitting control sub-signal, and the first light emittingcontrol sub-signal and the second light emitting control sub-signal arein opposite phases.

In the present disclosure, there is no special requirement for thespecific type of the light emitting control transistor P2. In thespecific embodiment illustrated in FIG. 2B, the light emitting controltransistor P2 is a P-type transistor, the first light emitting controlsub-signal is a low-level signal, and the second light emitting controlsub-signal is a high-level signal. In another embodiment, the lightemitting control transistor can be an N-type transistor, andaccordingly, the first light emitting control sub-signal is a high-levelsignal, and the second light emitting control sub-signal is a low-levelsignal.

In the present disclosure, there is no special requirement for thespecific structure of the storage sub-circuit 140, as long as the firstdata voltage written by the first data writing sub-circuit 110 and thesecond data voltage written by the second data writing sub-circuit 120can be stored, and the voltage at the first terminal of the storagesub-circuit 140 can be controlled when the second data voltage iswritten by the second data writing sub-circuit 120. In the specificembodiment illustrated in FIG. 2B, the storage sub-circuit 140 includesa storage capacitor C, a first terminal of the storage capacitor Cserves as the first terminal of the storage sub-circuit 140, and asecond terminal of the storage capacitor C serves as the second terminalof the storage sub-circuit 140.

In the specific embodiment illustrated in FIG. 2B, the first datawriting sub-circuit 110 includes the N-type data writing transistor N1and the P-type data writing transistor P1, the second data writingsub-circuit 120 includes the first data writing transistor P3, the resetsub-circuit 130 includes the first reset transistor N2 and the secondreset transistor N3, the storage sub-circuit 140 includes the storagecapacitor C, and the light emitting control sub-circuit 150 includes thelight emitting control transistor P2. For example, in the exampleillustrated in FIG. 2B, the N-type data writing transistor N1, the firstreset transistor N2, and the second reset transistor N3 are all N-typetransistors, and the P-type data writing transistor P1, the lightemitting control transistor P2, and the first data writing transistor P3are all P-type transistors.

The gate electrode of the N-type data writing transistor N1 iselectrically connected to a first N-type gate line G1, the gateelectrode of the P-type data writing transistor P1 is electricallyconnected to a first P-type gate line G2, the gate electrode of thefirst reset transistor N2 is electrically connected to the first resetcontrol signal line RS1, the gate electrode of the second resettransistor N3 is electrically connected to the first reset controlsignal line RS1, the gate electrode of the first data writing transistorP3 is electrically connected to the second gate line G3, and the gateelectrode of the light emitting control transistor P2 is electricallyconnected to the light emitting control signal line EM. The inputterminal of the first data writing sub-circuit 110 is electricallyconnected to the first data line D1, and the input terminal of thesecond data writing sub-circuit 120 is electrically connected to thesecond data line D2.

As illustrated in FIG. 3A, in the reset phase T1, the first N-type gateline G1 provides a third N-type data scanning signal of low level, thefirst P-type gate line G2 provides a third P-type data scanning signalof high level, the first reset control signal line RS1 provides a firstreset control sub-signal of high level, the light emitting controlsignal line EM provides a first light emitting control sub-signal ofhigh level, and neither the first data line D1 nor the second data lineD2 has a signal input. In the reset phase T1, no signal is provided tothe second gate line G3 or a high-level signal is provided to the secondgate line G3. Accordingly, in the reset phase T1, the N-type datawriting transistor N1 and the P-type data writing transistor P1 both areturned off, the first data writing transistor P3 and the light emittingcontrol transistor P2 are also turned off, and the first resettransistor N2 and the second reset transistor N3 are turned on, therebyresetting the second terminal of the storage capacitor C and the anodeof the light emitting element OLED. Resetting the second terminal of thestorage capacitor C and the anode of the light emitting element OLED canprevent the display device including the pixel circuit from generatingmotion blur during display.

In the charging phase T2, a first N-type data scanning signal of highlevel is provided to the first N-type gate line G1, a first P-type datascanning signal of low level is provided to the first P-type gate lineG2, a second reset control sub-signal of low level is provided to thefirst reset control signal line RS1, a first light emitting controlsub-signal of high level is provided to the light emitting controlsignal line EM, a first data voltage is provided to the first data lineD1, and no data voltage is provided to the second data line D2. In thecharging phase T2, a high-level signal is provided to the second gateline G3. In the charging phase T2, both the N-type data writingtransistor N1 and the P-type data writing transistor P1 are turned on,and the first data voltage is written into the first terminal of thestorage capacitor C. In addition, the first data writing transistor P3,the light emitting control transistor P2, the first reset transistor N2,and the second reset transistor N3 are all turned off, and at this time,the gate voltage of the driving transistor DTFT is a first voltage V1,that is, the first data voltage.

In the voltage jump phase T3, a fourth data scanning sub-signal of lowlevel is provided to the second gate line G3 to control the first datawriting transistor P3 to be turned on, so that the second data voltagecan be written into the second terminal of the storage capacitor Cthrough the second data line D2. In this case, due to the bootstrapeffect of the storage capacitor C, the voltage at the first terminal ofthe storage capacitor C, that is, the gate voltage of the drivingtransistor DTFT, rises to a second voltage V2, and the second voltage V2is a sum of the first data voltage and the second data voltage. Becauseall the transistors are silicon-based transistors, in order to ensurethat the voltage difference between any two electrodes of the N-typedata writing transistor N1 is within a threshold voltage range and thevoltage difference between any two electrodes of the P-type data writingtransistor P1 is within a threshold voltage range, accordingly, thevoltage of the signal written by the first N-type gate line G1 and thevoltage of the signal written by the first P-type gate line G2 should behigher than the respective voltages in the charging phase T2, asillustrated in FIG. 3A.

In the light emitting phase T4, a low-level signal is provided to thefirst N-type gate line G1, and a high-level signal is provided to thefirst P-type gate line G2, so as to ensure that both the N-type datawriting transistor N1 and the P-type data writing transistor P2 are inan off state. Furthermore, a high-level signal is provided to the secondgate line G3, so as to ensure that the first data writing transistor P3is turned off. In the light emitting phase T4, the gate voltage of thedriving transistor DTFT maintains as the second voltage V2. According tothe source following principle, the source voltage of the drivingtransistor DTFT (i.e., the voltage of the second electrode of thedriving transistor DTFT) is V2−Vth, where Vth is the threshold voltageof the driving transistor DTFT. In the present disclosure, because thesecond voltage V2 has a high voltage range, the source voltage of thedriving transistor DTFT (i.e., the voltage of the anode of the lightemitting element OLED) also has a high voltage range, thereby satisfyingthe requirements for realizing Mode One, which is a display mode of highcontrast ratio and high brightness.

What has been described above is the operation principle of the pixelcircuit to realize Mode One, which is a display mode of high contrastratio and high brightness, and the operation principle of the pixelcircuit to realize Mode Two, which is a display mode of high contrastratio and low brightness, is briefly described below.

In a case where Mode Two of the pixel circuit is realized, an operationperiod of the pixel circuit can include only the reset phase T1, thecharging phase T2, and the light emitting phase T4, without includingthe voltage jump phase T3. Of course, the present disclosure is notlimited thereto. The operation period of the pixel circuit can alsoinclude the voltage jump phase T3, and a difference lies in that avoltage of 0V is provided by the second data line D2 in the voltage jumpphase T3. Therefore, in the voltage jump phase T3, the voltage of thefirst N-type gate line G1 maintains as the voltage thereof in thecharging phase T2, the voltage of the first P-type gate line G2maintains as the voltage thereof in the charging phase T2, the gatevoltage of the driving transistor DTFT is still the first data voltageV1, and the source voltage of the driving transistor DTFT is V1−Vth.Because the first voltage V1 is lower than the second voltage V2, thesource voltage of the driving transistor DTFT is also lower than V2−Vth,thereby ensuring that the voltage difference between the anode and thecathode of the light emitting element OLED is relatively small andsatisfying the requirement of Mode Two of low brightness.

At least some embodiments of the present disclosure further provide adisplay panel, and FIG. 5 is a schematic diagram of a display panelprovided by some embodiments of the present disclosure.

For example, as illustrated in FIG. 5, a display panel 50 includes aplurality of pixel units 500. Each of the pixel units 500 is providedwith a pixel circuit 501 therein. For example, the pixel circuit 501 isthe pixel circuit 10 provided by any one of the above embodiments of thepresent disclosure. And each of the pixel units 500 further includes alight emitting element 502, the light emitting element 502 is the lightemitting element OLED described by any one of the above embodiments, andthe pixel circuit 501 is configured to drive the light emitting element502 to emit light.

For example, the plurality of pixel units 500 are arranged in aplurality of rows and a plurality of columns, the plurality of rows ofpixel units in the plurality of pixel units 500 are in one-to-onecorrespondence with a plurality of gate line groups, respectively, andthe plurality of columns of pixel units 500 in the plurality of pixelunits 500 are in one-to-one correspondence with a plurality of data linegroups, respectively.

As illustrated in FIG. 1B, FIG. 2A and FIG. 5, each gate line group ofthe plurality of gate line groups includes a first gate line and asecond gate line G3, the first gate line is configured to provide afirst data scanning signal, and the second gate line G3 is configured toprovide a second data scanning signal. Each gate line group furtherincludes a first reset control signal line RS1, a second reset controlsignal line RS2, and a light emitting control signal line EM. In a samerow of pixel units, the control terminal of the first data writingsub-circuit 110 in each of the pixel units 500 is electrically connectedto the first gate line to receive the first data scanning signal, thecontrol terminal of the second data writing sub-circuit 120 in each ofthe pixel units 500 is electrically connected to the second gate line G3to receive the second data scanning signal, the control terminal of thereset sub-circuit in each of the pixel units 500 is electricallyconnected to the first reset control signal line RS1 and the secondreset control signal line RS2, and the control terminal of the lightemitting control sub-circuit 150 in each of the pixel units 500 iselectrically connected to the light emitting control signal line EM.

Each data line group of the plurality of data line groups includes afirst data line D1 and a second data line D2, the first data line D1 isconfigured to provide a first data voltage, and the second data line D2is configured to provide a second data voltage. In a same column ofpixel units, the input terminal of the first data writing sub-circuit110 in each of the pixel units 500 is electrically connected to thefirst data line D1 to receive the first data voltage, and the inputterminal of the second data writing sub-circuit 120 in each of the pixelunits 500 is electrically connected to the second data line D2 toreceive the second data voltage.

For example, the control terminal of the first data writing sub-circuit110 includes an N-type control terminal (i.e., a first controlsub-terminal) and a P-type control terminal (i.e., a second controlsub-terminal), and the first data scanning signal includes a firstN-type data scanning signal and a first P-type data scanning signal.

Moreover, the first data writing sub-circuit 110 includes an N-type datawriting transistor N1 and a P-type data writing transistor N2.Accordingly, the first gate line includes a first gate sub-line G1(i.e., a first N-type gate line G1) and a second gate sub-line G2 (i.e.,a first P-type gate line G2). In a same row of pixel units, the N-typecontrol terminal in each of the pixel units is electrically connected tothe first N-type gate line G1, and the P-type control terminal in eachof the pixel units is electrically connected to the first P-type gateline G2.

At least some embodiments of the present disclosure further provide adisplay device, and FIG. 6 is a schematic diagram of a display deviceprovided by some embodiments of the present disclosure.

For example, as illustrated in FIG. 6, a display device 60 includes adisplay panel 600 and a photosensitive element 603. For example, thedisplay panel 600 is the above-mentioned display panel 50 provided bythe present disclosure, and the photosensitive element 603 is configuredto detect brightness of an environment in which the display device 60 islocated, generate a first trigger signal to control the display device60 to be in a first operation mode in a case where the brightness of theenvironment is higher than or equal to a preset brightness, and generatea second trigger signal to control the display device 60 to be in asecond operation mode in a case where the brightness of the environmentis lower than the preset brightness.

For example, the display brightness of the display device 60 in thefirst operation mode is higher than the display brightness of thedisplay device 60 in the second operation mode. The first operation modeis Mode One described above in FIG. 4A and FIG. 4B, and the secondoperation mode is Mode Two described above in FIG. 4A and FIG. 4B.

For example, as illustrated in FIG. 6, the display device 60 furtherincludes a data driver 601. The data driver 601 is electricallyconnected to the pixel circuit in the display panel 600 via the firstdata line D1 and the second data line D2, provide a first data voltageto the pixel circuit in the display panel 600 via the first data lineD1, and provide a second data voltage to the pixel circuit in thedisplay panel 600 via the second data line D2.

It should be noted that in a case where the display device 60 is in thefirst operation mode, in the charging phase, the data driver 601provides the first data voltage to the pixel circuit in the displaypanel 600 via the first data line D1; and in the voltage jump phase, thedata driver 601 provides the second data voltage to the pixel circuit inthe display panel 600 via the second data line D2. In a case where thedisplay device 60 is in the second operation mode, the data driver 601may only provide the first data voltage to the pixel circuit in thedisplay panel 600 via the first data line D1 in the charging phase.

For example, as illustrated in FIG. 6, the display device 60 furtherincludes a gate driver 602. The gate driver 602 is configured to providea first data scanning signal and a second data scanning signal to thepixel circuit in the display panel 600. For example, in a case where thedisplay device 60 is in the first operation mode, in the voltage jumpphase, the level of the first data scanning signal and the level of thesecond data scanning signal both jump. FIGS. 3A-3C illustrate severalschematic waveforms of the first data scanning signal and the seconddata scanning signal.

At least some embodiments of the present disclosure further provide amethod of driving a display device, and the method can drive any displaydevice provided by the present disclosure. FIG. 7 is a schematicflowchart of a method of driving a display device provided by someembodiments of the disclosure.

For example, in some embodiments, in a case where the photosensitiveelement generates the first trigger signal, as illustrated in FIGS.3A-3B, an operation period of the display panel includes a reset phaseT1, a charging phase T2, a voltage jump phase T3 and a light emittingphase T4. And as illustrated in FIG. 7, the method includes:

S10: in the charging phase, controlling the first data writingsub-circuit to write the first data voltage to the first terminal of thestorage sub-circuit;

S11: in the voltage jump phase, controlling the second data writingsub-circuit to write the second data voltage to the second terminal ofthe storage sub-circuit, so as to control the voltage at the firstterminal of the storage sub-circuit, in which the voltage at the firstterminal of the storage sub-circuit in the charging phase is differentfrom the voltage at the first terminal of the storage sub-circuit in thevoltage jump phase; and

S12: in the light emitting phase, the driving sub-circuit driving thelight emitting element to emit light based on the voltage at the firstterminal of the storage sub-circuit.

For example, in step S11, in a case where the driving transistor is anN-type transistor, the voltage at the first terminal of the storagesub-circuit in the charging phase is lower than the voltage at the firstterminal of the storage sub-circuit in the voltage jump phase; and in acase where the driving transistor is a P-type transistor, the voltage atthe first terminal of the storage sub-circuit in the charging phase ishigher than the voltage at the first terminal of the storage sub-circuitin the voltage jump phase.

For example, the method further includes: in the reset phase, writing afirst reference level signal to the second terminal of the storagesub-circuit through the reset sub-circuit, so as to reset the secondterminal of the storage sub-circuit, and writing the first referencelevel signal to the anode of the light emitting element through thereset sub-circuit, so as to reset the anode of the light emittingelement.

For example, in some embodiments, the display device can further includea driving circuit, which is configured to perform various steps in themethod described above. For example, the driving circuit is configuredfor following operations (e.g., providing signals).

In the reset phase T1, first reset control sub-signals are provided toall first reset control signal lines and all second reset control signallines, third N-type data scanning signals and third P-type data scanningsignals are provided to all first gate lines, fourth data scanningsub-signals are provided to all second gate lines, and second lightemitting control sub-signals are provided to all light emitting controlsignal lines.

In the charging phase T2, second reset control sub-signals are providedto all first reset control signal lines and all second reset controlsignal lines, a first N-type data scanning signal and a first P-typedata scanning signal are provided to each first gate line sequentiallyaccording to a predetermined scanning sequence, fourth data scanningsub-signals are provided to all second gate lines, second light emittingcontrol sub-signals are provided to all light emitting control signallines, and first data voltages are provided to all first data lines.

In the voltage jump phase T3, second reset control sub-signals areprovided to all first reset control signal lines and all second resetcontrol signal lines, fifth N-type data scanning signals and fifthP-type data scanning signals are provided to all first gate lines, athird data scanning sub-signal is provided to each second gate linesequentially according to the predetermined scanning sequence, secondlight emitting control sub-signals are provided to all light emittingcontrol signal lines, and second data voltages are provided to allsecond data lines. The second data voltage is higher than the first datavoltage by a preset value. For example, the first data scanningsub-signal can further include a fifth N-type data scanning signal, andthe second data scanning sub-signal can further include a fifth P-typedata scanning signal. As illustrated in FIG. 3A and FIG. 3B, the voltageof the fifth N-type data scanning signal is higher than the voltage ofthe first N-type data scanning signal and also higher than the voltageof the third N-type data scanning signal, and the voltage of the fifthP-type data scanning signal is higher than the voltage of the firstP-type data scanning signal and also higher than the voltage of thethird P-type data scanning signal.

In the light emitting phase T4, second reset control sub-signals areprovided to all first reset control signal lines and all second resetcontrol signal lines, third N-type data scanning signals and thirdP-type data scanning signals are provided to all first gate lines,fourth data scanning sub-signals are provided to all second gate lines,and first light emitting control sub-signals are provided to all lightemitting control signal lines.

It should be noted that in the light emitting phase T4, the drivingcircuit may also provide the fifth N-type data scanning signals and thefifth P-type data scanning signals to all the first gate lines.

The operation principle and beneficial effects of the pixel circuit havebeen described in detail above and are not described here again.

In the present disclosure, the “preset value” is not particularlylimited. For example, for a light emitting diode, the data voltage rangefor realizing high contrast ratio (e.g., 20000:1) and high brightness(>1500 nit) is 5V to 9V, while the data voltage range for realizing highcontrast ratio (e.g., 20000:1) and low brightness (375 nit) is 1V to 5V.Thus, in the present disclosure, the preset value is 3V.

It should be noted that in some other embodiments, in a case where thephotosensitive element generates the second trigger signal, an operationperiod of the display panel includes three phases: a reset phase, acharging phase and a light emitting phase.

For example, the method includes: in the charging phase, controlling thefirst data writing sub-circuit to write a first data voltage to thefirst terminal of the storage sub-circuit; and in the light emittingphase, the driving sub-circuit driving the light emitting element toemit light based on the voltage at the first terminal of the storagesub-circuit.

Alternatively, in a case where the photosensitive element generates thesecond trigger signal, an operation period of the display panel alsoincludes a reset phase, a charging phase, a voltage jump phase and alight emitting phase, and a difference lies in that the signals in thecharging phase are identical to the signals in the voltage jump phaseand the second data voltage is 0V in the voltage jump phase.

For example, in an embodiment where the control terminal of the firstdata writing sub-circuit includes an N-type control terminal and aP-type control terminal, and the first data writing sub-circuit includesan N-type data writing transistor and a P-type data writing transistor:

the first data scanning signal includes a first N-type data scanningsignal provided to the first N-type gate line, a first P-type datascanning signal provided to the first P-type gate line, a third N-typedata scanning signal provided to the first N-type gate line, and a thirdP-type data scanning signal provided to the first P-type gate line, thefirst N-type data scanning signal is a high-level signal, the thirdN-type data scanning signal is a low-level signal, the first P-type datascanning signal is a low-level signal, and the third P-type datascanning signal is a high-level signal; and

the first data scanning signal can further include a fifth N-type datascanning signal provided to the first N-type gate line and a fifthP-type data scanning signal provided to the first P-type gate line, thevoltage of the fifth N-type data scanning signal is higher than thevoltage of the first N-type data scanning signal, and the voltage of thefifth P-type data scanning signal is higher than the voltage of thefirst P-type data scanning signal. For example, in some examples, thevoltage of the fifth N-type data scanning signal is also higher than thevoltage of the third N-type data scanning signal, and the voltage of thefifth P-type data scanning signal is also higher than the voltage of thethird P-type data scanning signal.

In the present disclosure, the specific structure of the display device60 is not particularly limited. For example, the display device 60 canbe a near-eye device (e.g., VR glasses), so that a virtual scene can bebetter simulated according to the surrounding environment, which isbeneficial to improving the user's experience.

It should be understood that the above embodiments are merely exemplaryembodiments adopted to illustrate the principles of the presentdisclosure, but the present disclosure is not limited thereto. It isapparent to those skilled in the art that various modifications andimprovements can be made without departing from the spirit and essenceof the present disclosure, and these modifications and improvements arealso within the scope of protection of the present disclosure.

1: A pixel circuit, comprising: a driving sub-circuit, a first datawriting sub-circuit, a second data writing sub-circuit, and a storagesub-circuit, wherein the first data writing sub-circuit is electricallyconnected to a first terminal of the storage sub-circuit, and isconfigured to write a first data voltage to the first terminal of thestorage sub-circuit in a case of being turned on under control of afirst data scanning signal; the second data writing sub-circuit iselectrically connected to a second terminal of the storage sub-circuit,and is configured to write a second data voltage to the second terminalof the storage sub-circuit in a case of being turned on under control ofa second data scanning signal, so as to control a voltage at the firstterminal of the storage sub-circuit based on the second data voltage;the first terminal of the storage sub-circuit is further electricallyconnected to a control terminal of the driving sub-circuit; and thedriving sub-circuit is configured to drive a light emitting element toemit light under control of the voltage at the first terminal of thestorage sub-circuit. 2: The pixel circuit according to claim 1, whereinthe second data writing sub-circuit comprises a first data writingtransistor, a gate electrode of the first data writing transistor isconfigured to receive the second data scanning signal, a first electrodeof the first data writing transistor is configured to receive the seconddata voltage, and a second electrode of the first data writingtransistor is electrically connected to the second terminal of thestorage sub-circuit. 3: The pixel circuit according to claim 2, whereinthe first data writing transistor is turned on in a case where thesecond data scanning signal is at a first level, the first data writingtransistor is turned off in a case where the second data scanning signalis at a second level, and the first level is opposite to the secondlevel. 4: The pixel circuit according to claim 2, wherein the first datawriting transistor is a P-type transistor. 5: The pixel circuitaccording to claim 1, wherein a control terminal of the first datawriting sub-circuit is configured to receive the first data scanningsignal, the control terminal of the first data writing sub-circuitcomprises a first control sub-terminal and a second controlsub-terminal, the first data scanning signal comprises a first datascanning sub-signal and a second data scanning sub-signal, the firstcontrol sub-terminal is configured to receive the first data scanningsub-signal, and the second control sub-terminal is configured to receivethe second data scanning sub-signal. 6: The pixel circuit according toclaim 5, wherein the first data writing sub-circuit comprises an N-typedata writing transistor and a P-type data writing transistor, a firstelectrode of the N-type data writing transistor and a first electrode ofthe P-type data writing transistor are both configured to receive thefirst data voltage, a second electrode of the N-type data writingtransistor and a second electrode of the P-type data writing transistorare both electrically connected to the first terminal of the storagesub-circuit, the first control sub-terminal comprises a gate electrodeof the N-type data writing transistor, and the second controlsub-terminal comprises a gate electrode of the P-type data writingtransistor. 7: The pixel circuit according to claim 1, furthercomprising a reset sub-circuit, wherein a first output terminal of thereset sub-circuit is electrically connected to the second terminal ofthe storage sub-circuit, a second output terminal of the resetsub-circuit is electrically connected to an anode of the light emittingelement, and the reset sub-circuit is configured to reset the secondterminal of the storage sub-circuit under control of a first resetcontrol signal, and to reset the anode of the light emitting elementunder control of a second reset control signal. 8: The pixel circuitaccording to claim 7, wherein an input terminal of the reset sub-circuitis electrically connected to a first reference level signal terminal anda second reference level signal terminal, the reset sub-circuit isconfigured to write a first reference level signal of the firstreference level signal terminal to the second terminal of the storagesub-circuit under control of the first reset control signal, so as toreset the second terminal of the storage sub-circuit, and the resetsub-circuit is further configured to write a second reference levelsignal of the second reference level signal terminal to the anode of thelight emitting element under control of the second reset control signal,so as to reset the anode of the light emitting element. 9: The pixelcircuit according to claim 8, wherein the reset sub-circuit comprises afirst reset transistor and a second reset transistor, the input terminalof the reset sub-circuit comprises a first electrode of the first resettransistor and a first electrode of the second reset transistor, thefirst output terminal comprises a second electrode of the first resettransistor, the second output terminal comprises a second electrode ofthe second reset transistor, a gate electrode of the first resettransistor is configured to receive the first reset control signal, thefirst electrode of the first reset transistor is electrically connectedto the first reference level signal terminal, the second electrode ofthe first reset transistor is electrically connected to the secondterminal of the storage sub-circuit, a gate electrode of the secondreset transistor is configured to receive the second reset controlsignal, the first electrode of the second reset transistor iselectrically connected to the second reference level signal terminal,and the second electrode of the second reset transistor is electricallyconnected to the anode of the light emitting element. 10: The pixelcircuit according to claim 1, further comprising a light emittingcontrol sub-circuit, wherein the light emitting control sub-circuit isconfigured to electrically connect or disconnect the driving sub-circuitand the light emitting element under control of a light emitting controlsignal. 11: The pixel circuit according to claim 10, wherein the lightemitting control sub-circuit comprises a light emitting controltransistor, a gate electrode of the light emitting control transistor isconfigured to receive the light emitting control signal, a firstelectrode of the light emitting control transistor is electricallyconnected to a first level signal terminal, and a second electrode ofthe light emitting control transistor is electrically connected to thedriving sub-circuit. 12: The pixel circuit according to claim 10,wherein the driving sub-circuit comprises a driving transistor, a firstelectrode of the driving transistor is electrically connected to thelight emitting control sub-circuit, a second electrode of the drivingtransistor is electrically connected to an anode of the light emittingelement, and the control terminal of the driving sub-circuit comprises agate electrode of the driving transistor, the gate electrode of thedriving transistor is electrically connected to the first terminal ofthe storage sub-circuit, and a cathode of the light emitting element iselectrically connected to a second level signal terminal. 13: The pixelcircuit according to claim 1, wherein the storage sub-circuit comprisesa storage capacitor, the first terminal of the storage sub-circuitcomprises a first terminal of the storage capacitor, and the secondterminal of the storage sub-circuit comprises a second terminal of thestorage capacitor. 14: A display panel, comprising the pixel circuitaccording to claim
 1. 15: The display panel according to claim 14,further comprising a plurality of pixel units, wherein the plurality ofpixel units are arranged in a plurality of rows and a plurality ofcolumns, and the pixel circuit is disposed in at least one of theplurality of pixel units. 16: The display panel according to claim 15,wherein the plurality of rows of pixel units in the plurality of pixelunits are in one-to-one correspondence with a plurality of gate linegroups, respectively, and the plurality of columns of pixel units in theplurality of pixel units are in one-to-one correspondence with aplurality of data line groups, respectively; each of the plurality ofgate line groups comprises a first gate line and a second gate line, thefirst gate line is configured to provide the first data scanning signal,and the second gate line is configured to provide the second datascanning signal; in pixel units of a same row, the first data writingsub-circuit in each of the pixel units is electrically connected to thefirst gate line to receive the first data scanning signal, and thesecond data writing sub-circuit in each of the pixel units iselectrically connected to the second gate line to receive the seconddata scanning signal; each of the plurality of data line groupscomprises a first data line and a second data line, the first data lineis configured to provide the first data voltage, and the second dataline is configured to provide the second data voltage; and in pixelunits of a same column, the first data writing sub-circuit in each ofthe pixel units is electrically connected to the first data line toreceive the first data voltage, and the second data writing sub-circuitin each of the pixel units is electrically connected to the second dataline to receive the second data voltage. 17: The display panel accordingto claim 16, wherein, in a case where a control terminal of the firstdata writing sub-circuit comprises a first control sub-terminal and asecond control sub-terminal, the first gate line comprises a first gatesub-line and a second gate sub-line, and in the pixel units of the samerow, the first control sub-terminal of the first data writingsub-circuit in each of the pixel units is electrically connected to thefirst gate sub-line, and the second control sub-terminal of the firstdata writing sub-circuit in each of the pixel units is electricallyconnected to the second gate sub-line. 18: A display device, comprisingthe display panel according to claim
 14. 19: The display deviceaccording to claim 18, further comprising a photosensitive element,wherein the photosensitive element is configured to detect brightness ofan environment in which the display device is located, generate a firsttrigger signal to control the display device to be in a first operationmode in a case where the brightness is higher than or equal to a presetbrightness, and generate a second trigger signal to control the displaydevice to be in a second operation mode in a case where the brightnessis lower than the preset brightness. 20-22. (canceled) 23: A method ofdriving the display device according to claim 19, wherein, in a casewhere the photosensitive element generates the first trigger signal, anoperation period of the display panel comprises a charging phase, avoltage jump phase, and a light emitting phase, and the methodcomprises: in the charging phase, controlling the first data writingsub-circuit to write the first data voltage to the first terminal of thestorage sub-circuit; in the voltage jump phase, controlling the seconddata writing sub-circuit to write the second data voltage to the secondterminal of the storage sub-circuit, so as to control the voltage at thefirst terminal of the storage sub-circuit, wherein the voltage at thefirst terminal of the storage sub-circuit during the charging phase isdifferent from the voltage at the first terminal of the storagesub-circuit during the voltage jump phase; and in the light emittingphase, the driving sub-circuit driving the light emitting element toemit light based on the voltage at the first terminal of the storagesub-circuit.
 24. (canceled)